Packet Processing with PowerPC on the NetFPGA

The NetFPGA[2] community has made significant progress in making experimentation with high-speed reconfigurable networking hardware[6] easier and more accessible. They have provided an environment in which hardware modules implemented in Verilog can work together with software running on a host CPU using the primitives of DMA packet transfer and register access over the PCI bus. The NetFPGA’s Virtex-II Pro has two PowerPC hard core processors which have not been used in any reported NetFPGA projects. Putting these hard core processors to work can yield certain benefits. First, the PCI bus severely limits the throughput of packet transfers between the NetFPGA hardware and the host CPU. An on-chip processor would not suffer from this limitation. Second, running the software on an on-chip processor could significantly improve latency of packet transfer and register access. Third, the flexibility of an onchip general-purpose processor with decent performance opens up new possibilities for experimentation, while also making it easier for non-hardware experts to try their ideas on the NetFPGA. Finally, since they are already taking up space on the chip whether they are used or not, we might as well use them. There are naturally some costs and limitations associated with using these processors, and one goal of this project is to attempt to quantify them. Another goal is to make it easier for others in the NetFPGA community to utilize these processors.